library IEEE;
use IEEE.std_logic_1164.all;

entity testbench_adder_n is
end testbench_adder_n;

architecture behavioral of testbench_adder_n is

    constant N     : integer := 4;

    signal a    : std_logic_vector(N-1 downto 0); 
    signal b    : std_logic_vector(N-1 downto 0);
    signal cin  : std_logic;
    signal y    : std_logic_vector(N-1 downto 0);
    signal cout : std_logic;

    component adder_n
    generic (N : integer := 4);
    port (
        a_i    : in  std_logic_vector(N-1 downto 0);
        b_i    : in  std_logic_vector(N-1 downto 0);
        cin_i  : in  std_logic;
        y_o    : out std_logic_vector(N-1 downto 0);
        cout_o : out std_logic);
    end component;
  
begin  -- behavioral

    adder_n_inst : adder_n generic map (
        N => N
    ) port map (
        a_i    => a,
        b_i    => b,
        cin_i  => cin,
        y_o    => y,
        cout_o => cout
    );

    test : process
    begin  -- process
        a    <= x"0";
        b    <= x"0";
        cin  <= '0';

        wait for 10 ns;

        a    <= x"F";
        b    <= x"7";
        cin  <= '0';

        wait for 10 ns;

        a    <= x"B";
        b    <= x"8";
        cin  <= '1';

        wait for 10 ns;

        a    <= x"A";
        b    <= x"6";
        cin  <= '0';

        wait for 10 ns;
        wait;
    end process;

end behavioral;

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